1. Field of the Disclosure
The present disclosure generally relates to the formation of semiconductor devices, and, more specifically, to various methods of forming features having differing pitch spacing and critical dimensions.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element used in manufacturing such integrated circuit devices. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
Numerous processing operations are performed in a very detailed sequence, or process flow, to form integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc. In general, the formation of integrated circuit devices involves, among other things, the formation of various layers of material and patterning or removing portions of those layers of material to define a desired structure, such as a gate electrode, a sidewall spacer, etc. Device designers have been very successful in improving the electrical performance capabilities of transistor devices, primarily by reducing the size of or “scaling” various components of the transistor, such as the gate length of the transistors. In fact, device dimensions on modern day transistors have been reduced to the point where direct patterning of such features is very difficult using existing photolithography tools and technology. Thus, device designers have employed various techniques to pattern very small features.
Device designers design chips comprised of transistors having different gate lengths formed on the same semiconductor substrate. For example, in the logic circuits of an integrated circuit product where switching speed and high performance is paramount, an integrated circuit product may be designed so as to only use high-performance, relatively smaller gate length transistor devices in such logic circuits. However, in other regions of the integrated circuit product where switching speed is not as critical, e.g., input/output circuits, the product may be designed so as to use transistor devices having relatively larger gate lengths in an effort to reduce the overall power consumption of the integrated circuit product.
The present disclosure is directed to various methods of patterning features that have differing pitch spacing and critical dimensions, such as gate lengths, wherein the features may be part of an integrated circuit product.